1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device improved in a method of applying stress to bit lines at a test time.
2. Description of the Related Art
A nonvolatile semiconductor memory, for example, a NOR-type flash memory is provided with a dedicated circuit for exclusive use in a bit line stress test in order to carry out the same test (all bits, even bits, odd bits) at a die sort test time. The dedicated circuit for the bit line stress test includes a load circuit for stress test, a transistor for applying stress, a decode circuit which selects the transistor for applying stress and a charging wiring.
When the NOR-type flash memory has a plurality of banks, the dedicated circuit for the bit line stress test needs the load circuit in every bank and when the NOR-type flash memory has a plurality of blocks, it needs the transistor for applying stress and the decode circuit which selects the transistor, in every block.
The NOR-type flash memory is improved in downsizing and enlarging capacity. Building the dedicated circuit for the bit line stress test into a memory chip disturbs the downsizing and the enlargement of capacity.